1. Technical Field
The present invention relates to an A/D (analog-digital) conversion apparatus which performs A/D conversion of an analog input signal by using a pulse delay circuit, in particular, relates to an output changing method of changing output of an A/D converted value and an A/D conversion apparatus realizing the method.
2. Related Art
An A/D conversion apparatus is known which uses a pulse delay circuit, which is configured by connecting in a ring shape a plurality of delay units including various gate circuits such as an inverter, to convert an analog input signal to numeric data (see, for example, JP-A-5-259907).
In this type of A/D conversion apparatus, an analog input signal subject to A/D conversion is applied as power supply voltage of the delay units configuring the pulse delay circuit to vary delay time caused when a pulse signal passes the delay units depending on the signal level of the analog input signal.
Then, an encoding circuit counts the number of stages of the delay units, through which the pulse signal has passed within a predetermined sampling time, to output the count value as an A/D converted value of the analog input signal.
In the above A/D conversion apparatus, the delay units in the pulse delay circuit operate using the analog input signal as the power supply voltage. Hence, the signal levels of the pulse signals outputted from the delay units are voltage values corresponding to the analog input signal.
Hence, the signal levels of the pulse signals outputted from the delay unit vary. If the varied signal levels deviate from a normal voltage range within which the encoding circuit can count the number of stages of the delay units, through which the pulse signal has passed, errors are caused in the A/D converted value.
That is, the encoding circuit detects a rising (or falling) edge of the pulse signal outputted from the delay unit when an output of the delay unit changes form a low level to a high level (or from a high level to a low level). Then, the number of stages of the delay units is detected, through which the pulse signal has passed in the pulse delay circuit, based on the number of times of detection of edges and the positions of the delay units which have detected the edges.
Hence, if the signal level of the pulse signal outputted from the delay unit in the pulse delay circuit is equal to or more than a threshold voltage by which the encoding circuit can distinguish between the low level and the high level of the pulse signal, the encoding circuit can detect the edge of the pulse signal.
However, if the voltage level of the analog input signal is lower, and the signal level of the pulse signal outputted from the delay unit in the pulse delay circuit decreases below the threshold voltage of the encoding circuit, the encoding circuit cannot correctly detect the number of stages of the delays unit through which the pulse signal has passed.
In addition, if the voltage level of the analog input signal is higher, the delay time is shortened which is caused when the pulse signal passes through the delay units in the pulse delay circuit.
Hence, if the voltage level of the analog input signal becomes higher, the speed of the pulse signal in the pulse delay circuit becomes too high compared with the operating time required for detecting the number of stages of the delay units by the encoding circuit. Accordingly, the encoding circuit may not correctly detect the number of stages of the delay units.
Hence, in the above A/D conversion apparatus, as shown in FIG. 9, if the voltage level of an analog input signal Vin deviates from a normal operation range of the encoding circuit, the encoding circuit malfunctions. Thereby, A/D conversion cannot be correctly performed for the analog input signal Vin.